1. Field of the Invention
The present invention relates to dynamic memory devices and, more specifically, to a dynamic semiconductor memory device improved to raise voltage level of word lines.
2. Description of the Background Art
Recently, in order to meet the demand of microelectronics implementation of various devices in industry and in civil equipments, VLSIs (Very Large Scale Integrated circuits) having larger scale than LSIs (Large Scale Integrated circuits) have been developed and come to be commercially used.
FIG. 6 is a block diagram of a dynamic RAM (Random Access Memory) formed of such a LSI or VLSI. Referring to FIG. 6, the dynamic RAM includes a memory array 1, a word line driving signal generating circuit 2 for generating a signal R.sub.X for driving word lines WL included in the memory array 1, and a word line boost circuit 3 for boosting the word line driving signal R.sub.X. The word line driving signal generating circuit 2 is connected to receive a RAS (Row Address Strobe) signal through a RAS buffer 4. A row decoder 1a, a sense amplifier 1b, a column decoder 1c and an I/O gate 1d are connected to the memory array 1. The dynamic RAM is accessed by row address signals.multidot.column address signals output from an address buffer 5 to the memory array 1.
The operation will be described in the following.
Generally, the dynamic RAM receives time sequentially the row and column address signals through terminals A0 to A9. First, the respective address signals are input at an edge timing at which the RAS signal and a CAS (Column Address Strobe) signal from the CAS buffer 6 fall, respectively. Then a word line is selected by the row address signal, and by a word line driving signal R.sub.XB which has been boosted, the word line is activated. A bit line is selected by the column address signal. Consequently, in reading operation, a signal stored in the memory cell is applied to the bit line. The signal applied to the bit line is output through the I/O gate 1d.fwdarw.output buffer 7.fwdarw.data output terminal Dout. In writing, in response to a write enable signal WE from a write buffer 8, input data is applied to the memory cell through the data input terminal Din.fwdarw.input buffer 9.fwdarw.I/O gate 1d.
FIG. 7 is a block diagram showing the memory cell, the row decoder and the boost circuit. Referring to FIG. 7, the memory cell MC includes a capacitor C.sub.S and a switching transistor Q.sub.M connected to the word line WL and to the bit line BL. By applying a voltage of high level "1" or low level "0" to the capacitor C.sub.S, a signal is stored. When the word line WL is activated, the transistor Q.sub.M is turned on. When the transistor Q.sub.M is turned on, the charges stored in the capacitor C.sub.S are applied to the bit line BL which has been at a floating state. The stray capacitance of the bit line BL is about ten times the capacitance of the capacitor C.sub.S. Therefore, a potential change as small as about several hundred milli-volts appears on the bit line BL. The potential change is amplified by a sense amplifier 1b and is applied to the I/O gate 1d for reading/writing.
By the above described series of operations, a signal from a designated memory cell MC of the plurality of memory cells MCs of the memory array 1 is applied through the I/O gate 1d to the output buffer 7. In writing, in response to a write enable signal WE, the write buffer 8 drives an input buffer 9, and data applied through the input buffer 9 is written through the I/O gate to the memory cell MC.
The word line boost circuit will be described in the following.
When the word line WL is changed to the high level, the transistor Q.sub.M is turned on. If this high level is the supply voltage level V.sub.cc, the high storage level is reduced by the threshold voltage V.sub.TH of the transistor Q.sub.M. The ratio of this loss is normally about 20%, which is not so high as to immediately cause malfunction. However, if the supply voltage level becomes lower, the loss becomes greater comparatively, reducing operation margin. The word line boost circuit is used to solve this problem. This circuit serves to raise the voltage level of the word line to be higher than the sum of the supply voltage level V.sub.cc and the threshold value V.sub.TH of the transistor Q.sub.M. The word line boost circuit 3 of FIG. 7 attains this object. The word line boost circuit 3 includes a charge line 31 for charging the word line WL, a delay circuit 32 connected to receive the word line driving circuit R.sub.X, and a boosting capacitor 33 connected between the charge line 31 and the output of the delay circuit 32.
FIG. 8 is a timing diagram illustrating the operation of the word line boost circuit 3 shown in FIG. 7.
Referring to FIGS. 7 and 8, the operation of the word line boost circuit 3 will be described. At time T0, the word line driving signal R.sub.X changes to the high level. The output signal R.sub.XB is delayed by the delay circuit 32 and changes to the high level at time T1. Consequently, the voltage level of the output signal R.sub.XB is raised to a level V.sub.cc +V.alpha. due to the capacitance coupling of the capacitor 33, which level is higher than the supply voltage level V.sub.cc. By appropriately setting the capacitance value of the capacitor 33, V.alpha. is made higher than the threshold voltage V.sub.TH of the transistor Q.sub.M. In this manner, the word line driving signal R.sub.X is boosted, providing the boosted word line driving signal R.sub.XB. The high level signal R.sub.XB is output from an output which is in a floating state, separated from the power supply. The boosted word line driving signal R.sub.XB is applied to the memory array 1 though the row decoder 1a, and activates the word line WL selected by the row decoder 1a.
Returning to FIG. 7, the row decoder will be described. Referring to FIG. 7, the row decoder 1a includes a plurality of unit row decoders RD each for activating one of a plurality of rows. For the simplicity of description, a row decoder for one row is shown. The unit row decoder RD includes an NAND gate 11 connected to receive row decoder address signals RA1 to RA9, an inverter 12 connected to the output thereof, and three N channel transistors Q.sub.AK, Q.sub.BK and Q.sub.CK.
In operation, when this unit row decoder RD is selected, for example, the row address signals RA0 to RA9 are set to high level, and the NAND gate 11 outputs a low level signal. This signal is inverted by the inverter 12 and applied to the gate of the transistor Q.sub.BK and to the gate of the transistor Q.sub.CK. Consequently, the transistor Q.sub.BK is turned on, and the boosted word line driving signal R.sub.XB is applied to the word line WL.sub.K through the transistor Q.sub.BK.
However, in the conventional word line boost circuit 3, when there is a leak in the capacitor 33, the level of the word line driving signal R.sub.XB gradually lowers, as shown in FIG. 9. Especially when the RAS signal has a long period (longer than several ten .mu.sec), the level of the boosted word line driving signal R.sub.XB becomes too low to activate the word line WL. Therefore, when the write enable signal WE falls to write new data to the memory cell MC near the end of the period of the RAS signal, the channel of the transistor Q.sub.M is not perfectly formed, since the level of the word becomes very low. Therefore, data can not be written to the memory cell. In other words, the conventional boost circuit has small write margin.